1. Field of the Invention
The present invention relates to a circuit and a method for a memory test. More particularly, the present invention relates to a circuit and a method for a memory built in self test (MBIST).
2. Description of the Related Art
Over 70% of today's chip designs implement embedded memories, and the embedded memories are consuming more and more die area. It is estimated that in the year 2010 embedded memories will occupy more than 90% of total area of system-on-chip (SOC) designs. Therefore test of embedded memories is becoming an important issue. If the memory test is handled by external devices, a chip has to dedicate a lot of pins for transmitting signals of the test. The placing and routing (P&R) of transmission tracks connecting the dedicated pins and the embedded memories undesirably increase cost and complexity of SOC designs. In contrast, memory built in self test (MBIST) is a very efficient way to test embedded memories with a relatively low area and design impact.
FIG. 1 is a schematic diagram showing a conventional MBIST circuit 100. The test controller 101 controls the MBIST process by providing address signals, data signals and memory control signals to the embedded memory block 109. The memory block 109 provides data output signals in response to the signals from the test controller 101.
The test controller 101 comprises a finite state machine (FSM) 102, an address generator 103, a data generator 104, a control generator 105 and a comparator 106. In brief, the address generator 103 provides the address signals. The data generator 104 provides the data signals. The control generator 105 provides the memory control signals. The comparator 106 verifies data output signals from the memory block 109 based on the signals provided by the test controller 101. The finite state machine 102 controls and coordinates the other components of the test controller 101 in order to perform the MBIST.
Apart from the MBIST, during normal operations the memory block 109 provides data output signals in response to address signals, data signals and memory control signals provided by the system logic 107. The multiplexers 108 ensures that the memory block 109 receives signals provided by the test controller 101 during an MBIST and receives signals provided by the system logic 107 during normal operations.
MBIST is usually performed in groups. A group includes a test controller and multiple embedded memory blocks. For example, FIG. 2 is a schematic diagram showing a conventional MBIST circuit 200 for such a group. The test controller 202 provides address signals, data signals and memory control signals through the multiplexers 201 to the memory blocks 1˜n and receives data output signals from the memory blocks 1˜n. Each memory block 1˜n uses an individual set of transmission tracks to receive signals from the test controller 202 and to provide data output signals to the test controller 202. The test controller 202 also delivers address signals, data signals and memory control signals from the system logic 203 through the multiplexers 201 to the memory blocks 1˜n.
Because each of the memory blocks 1˜n uses an individual set of transmission tracks in the MBIST circuit 200, as the number of memory blocks increase, chip area can be congested with transmission tracks, complicating P&R effort.
FIG. 3 is a schematic diagram showing another conventional MBIST circuit 300. The difference between the MBIST circuit 200 and the MBIST circuit 300 is that the multiplexers 201 in the MBIST circuit 200 are attached to the test controller 202 while the multiplexers 301 in the MBIST circuit 300 are placed apart from the test controller 302. The multiplexers 301 receive signals directly from the system logic (not shown in FIG. 3). Although the test controller 302 does not have to deliver signals from the system logic as the test controller 202 does, the MBIST circuit 300 still faces the same problem of routing congestion caused by too many transmission tracks.